Skip to content
View kasinath's full-sized avatar

Highlights

  • Pro

Block or report kasinath

Block user

Prevent this user from interacting with your repositories and sending you notifications. Learn more about blocking users.

You must be logged in to block users.

Maximum 250 characters. Please don’t include any personal information such as legal names or email addresses. Markdown is supported. This note will only be visible to you.
Report abuse

Contact GitHub support about this user’s behavior. Learn more about reporting abuse.

Report abuse
kasinath/README.md

Hi there 👋 I'm Kasinath (KASI)

Project Engineer @ C-DAC | M.Tech Micro & Nano Electronics

Digital Design Engineer focused on processor architecture, RTL development, FPGA prototyping, and ASIC design:

  • RISC-V Processor Design
  • Computer Architecture
  • ASIC & FPGA Design
  • RTL Design & Verification
  • Embedded Systems
  • High-Performance Computing (HPC)

Currently Working On

  • Debug Architecture for RISC-V Processors
  • Computer Architecture & ISA Design
  • Open-source RTL Projects

Tech Stack

Verilog • SystemVerilog • Embedded C • Python • Vivado • Cadence • Synopsys • Git • Linux

Interests

Processor Design • Microarchitecture • SoC Design • VLSI • Semiconductor R&D

📫 Email: kasinathp2002@gmail.com

Popular repositories Loading

  1. kasinath kasinath Public

    My personal repository

  2. skills-copilot-codespaces-vscode skills-copilot-codespaces-vscode Public

    My clone repository

  3. Spoon-Knife Spoon-Knife Public

    Forked from octocat/Spoon-Knife

    This repo is for demonstration purposes only.

    HTML

  4. tiny-gpu tiny-gpu Public

    Forked from adam-maj/tiny-gpu

    A minimal GPU design in Verilog to learn how GPUs work from the ground up

    SystemVerilog

  5. odysseus odysseus Public

    Forked from arcahyadi/odysseus

    Self-hosted AI workspace.

    Python

  6. LF-Building-a-RISC-V-CPU-Core LF-Building-a-RISC-V-CPU-Core Public

    Forked from stevehoover/LF-Building-a-RISC-V-CPU-Core

    TL-Verilog