Abolfazl “Abish” Sajadi

Digital Hardware Engineer · Hardware Security

Digital hardware engineer completing a PhD at Leiden University, with hands-on experience in RTL/SoC design, RISC-V integration, FPGA prototyping, ASIC implementation, and hardware security. Most recently: designed the PROACT dual-core RISC-V cryptographic SoC, taped out in GlobalFoundries 22 nm (22FDX).

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Portrait of Abolfazl Sajadi
Abolfazl “Abish” Sajadi Leiden University (LIACS)

About

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I'm a digital hardware engineer completing my PhD at LIACS, Leiden University, working on hardware security and digital IC design in the PROACT project. As the project's chip designer I took its dual-core RISC-V cryptographic SoC from architecture to silicon — full-chip integration and all peripheral & control logic, FPGA prototypes first, then synthesis and verification for a 22 nm GlobalFoundries 22FDX tape-out, with place-and-route and sign-off done with the imec team. The full breakdown is in The PROACT Chip below.

I also developed the chip's software stack — C and Python libraries and a control GUI — and its documentation, and designed a ChipWhisperer CW308 target board in Altium with an automated CPA/TVLA side-channel flow. I'm strongest in the front-end (RTL design, synthesis, functional verification), with hands-on FPGA prototyping, software and side-channel board experience.

Career & Education

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FIG. 1 — CAREER & EDUCATION TIMING DIAGRAM, 2011–2027 · drag sideways to see the full diagram ARB nationwide B.Sc. entrance exam ISR mandatory national service (4 mo) + M.Sc. entrance exam CDC visa & relocation, IR → NL

Experience

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AUG 2022 – FEB 2027 · ONGOING

Doctoral Researcher — Digital IC & Hardware Security

Leiden University (LIACS) · Leiden, NL

  • Designed the full PROACT dual-core RISC-V cryptographic SoC — RTL architecture, full-chip integration and all peripheral & control logic, with the Ibex core and three crypto co-processors integrated as third-party/partner IP (details in The PROACT Chip).
  • Prototyped and validated the SoC on Xilinx Artix-7 and Zynq-7000 FPGAs using SPI/UART interfaces; developed C and Python libraries, a control GUI, and user documentation.
  • Synthesized the SoC for GlobalFoundries 22FDX using Cadence Genus and performed functional and SDF-annotated gate-level verification in Xcelium.
  • Contributed to ASIC physical implementation and MPW tape-out with the imec team, including place-and-route, sign-off, GDSII generation, and design of the 28-pin DIP package bonding diagram.
  • Built a ChipWhisperer CW308 target board (Altium) and automated CPA/TVLA side-channel evaluation of AES on the RISC-V core.

2018 – 2021

M.Sc. + Research Assistant — Digital Electronic Systems

University of Tehran (DVD-ES Lab) · Tehran, IR

  • M.Sc. (GPA 18.28/20, ranked 1st) alongside full-time research at the DVD-ES Lab: designed and evaluated ML-resistant PUF authentication protocols (DC-PUF, SQ-PUF) on FPGA and implemented CNN/SVM modeling attacks in Python (published in J. Network & Computer Applications).

2020 – 2021

Hardware Engineer

Ryan iMachines

  • ML-algorithm design, RTL (Verilog) implementation, test and debug.

2020

Hardware Engineer (project-based)

Shahab Co.

  • Home Meter Monitoring Device: ESP32 + AVR (ATmega8) firmware and a custom PCB designed in Altium — see project card.

EARLIER

Private tutor, VHDL & FPGA — OstadSalam.ir (2020–21) · Web designer — ETC Co. (2019), four commercial WordPress sites

The PROACT Chip

req

A hardware-security research SoC taken from RTL to a fabricated 22 nm ASIC — dual 32-bit RISC-V architecture: a controller core plus an Ibex software-executor core, with AES, Ascon and Xoodyak crypto co-processors.

2.009 × 2.055 mm²die, incl. scribe
GF 22FDX22 nm process
Europractice MPW50 packaged units
Taped outfabrication in progress

// my role

  • Full-chip design & integration: RTL architecture, full-chip integration and all peripheral & control logic (SPI bridge, configurable UART, control/status registers, PRNG) — integrating the Ibex core and the AES, Ascon and Xoodyak co-processors as third-party IP.
  • FPGA prototyping: ZYBO and PYNQ-Z2 boards.
  • Software stack: C/Python libraries, control GUI, and documentation.
// asic flow & side-channel platform
  • Synthesis in Cadence Genus for GlobalFoundries 22FDX; functional and SDF-annotated gate-level verification in Xcelium.
  • Place-and-route, sign-off and GDSII with the imec team; 28-pin ceramic DIP bonding diagram.
  • Custom ChipWhisperer CW308 target board (Altium, 4-layer, 0.01 Ω shunt) with an automated CPA/TVLA evaluation flow.
Stylized floorplan of the PROACT test chip — 2.009 × 2.055 mm² die in GlobalFoundries 22FDX. I designed the full SoC — the RTL architecture, full-chip integration and all peripheral & control logic (SPI, UART, CSR, PRNG, amber) — integrating third-party IP such as the Ibex RISC-V core and the AES, Ascon and Xoodyak cryptographic co-processors (grey), from RTL through FPGA prototyping to tape-out.
  • Peripheral & control RTL I designed — SPI, UART, CSR, PRNG
  • Integrated IP — Ibex RISC-V core, AES/Ascon/Xoodyak co-processors

Selected Projects

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OPEN-SOURCE / ACM CF '26

ASSESS — pre-silicon side-channel leakage analysis

A cycle-accurate methodology that localizes gate-level side-channel leakage from toggle activity, fast enough for routine checks during iterative ASIC design; benchmarked against RTL-PAT, PATCH and ACA on RISC-V/AES designs.

Paper (ACM CF Companion '26)

VIVADO HLS / B.SC. THESIS

Real-time object detection & tracking on Zynq-7000

Real-time object detection and tracking on a ZYBO Zynq-7000 — HDMI video in, color-range filtering, and distance estimation from object size, with simultaneous LED-matrix and VGA output plus UART telemetry. Verified in MATLAB/OpenCV, then synthesized to hardware with HLS + Vivado.

Real-time object detection & tracking system on a ZYBO Zynq-7000: camera and HDMI input, color-based detection, LED-matrix and VGA output

View B.Sc. thesis demos

RTL / QUARTUS / CYCLONE II

CNN accelerator on FPGA

RTL implementation of a quantized tiny convolutional-network accelerator (MNIST), validated against a Keras reference model and brought up on an Altera Cyclone II board.

ESP32 / AVR / ALTIUM · 2020

Home meter monitoring device

Design & implementation of a Home Meter Monitoring Device — project-based (Arduino, AVR, PCB). Implemented on ESP32 and AVR (ATmega8) microcontrollers, with a custom PCB designed in Altium Designer (2020). Delivered for Shahab Co.

Three custom ESP32-CAM-based monitoring PCBs designed in Altium

Publications

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Each record includes the paper PDF, its publisher page, and a detailed AI-readable memory with methods, evidence, limitations, and citation context.

  1. JOURNAL2023

    Journal of Network and Computer Applications, vol. 217, article 103693, 2023 · DOI 10.1016/j.jnca.2023.103693

    Read PDF DOI / publisher AI paper memory
    Paper explanation and citation context

    Core contribution. A stateful Arbiter-PUF authentication protocol in which each effective challenge depends on the current challenge, a random bit, and the preceding authenticated response, making harvested challenge-response pairs harder to model.

    Key evidence
    At 400,000 CRPs, reported prediction accuracy was 51.55% for logistic regression, 52.56% for ANN, and 56.27% for CNN; measured uniformity was 51.57% and uniqueness 49.23%.
    Cite this for
    Stateful or machine-learning-resistant PUFs, lightweight IoT authentication, and dependency-chain challenge obfuscation.
    Scope
    The results are empirical under the evaluated attacks; secure enrollment and correct protocol-state synchronization are assumed, not proven universally.

  2. JOURNAL2023PERSIAN

    Iranian Journal of Electrical and Computer Engineering, vol. 21, no. 3, pp. 219–226, 2023

    Read PDF Publisher record AI paper memory
    Paper explanation and citation context

    Core contribution. SQ-PUF uses selected sequence-dependent modules so that the effective challenge depends on prior state and randomness, combining an LFSR with a single Arbiter PUF for lightweight authentication.

    Key evidence
    For the principal 400,000-CRP experiment, reported accuracies were 52.14% for logistic regression, 52.40% for ANN, and 50.22% for SVM; uniformity was 50.561% and uniqueness 49.101%.
    Cite this for
    Sequence-dependent PUF constructions and lightweight authentication designed to resist evaluated machine-learning attacks.
    Scope
    The paper is in Persian and reports simulation-based results for specified attack models; secure enrollment and synchronized state remain system assumptions.

  3. CONFERENCE2026

    ACM Computing Frontiers (CF Companion '26), 2026 · DOI 10.1145/3801488.3807896

    Read PDF DOI / publisher AI paper memory
    Paper explanation and citation context

    Core contribution. After comparing RTL-PAT, PATCH, and ACA, the paper introduces ASSESS: a cycle-accurate VCD plus one-off average-power scan that localizes pre-silicon side-channel leakage without repeatedly storing and processing full time-series traces.

    Key evidence
    On a 600-cycle Ibex case, ASSESS completed in 1 h 53 min 9 s versus 72 d 15 h 31 min for ACA, a reported 960× speedup; the corresponding PATCH comparison reports 1,030×.
    Cite this for
    Pre-silicon leakage localization, Leakage Impact Factor analysis, gate-level side-channel assessment, or ASSESS runtime improvements.
    Scope
    Results use GF22FDX gate-level Ibex/Tiny-AES and AES-coprocessor cases; the workflow requires a technology library and power-analysis tooling.

  4. CONFERENCE2024

    IEEE Nordic Circuits and Systems Conference (NorCAS), 2024 · DOI 10.1109/NorCAS64408.2024.10752477

    Read PDF DOI / publisher AI paper memory
    Paper explanation and citation context

    Core contribution. A same-platform security-and-cost comparison of Mask-AES, software and hardware noise generation, Secure-Ibex, and CoCo-Ibex countermeasures for AES software on RISC-V SoCs.

    Key evidence
    The baseline key was recovered at about 250 traces; Mask-AES resisted recovery through 21,000 traces at 2.03× code and 1.47× time, while Secure-Ibex resisted 18,000 traces at 1.41×–5.13× time.
    Cite this for
    Side-channel security/cost trade-offs, AES on RISC-V, masking, noise generation, secure processors, or compositional countermeasures.
    Scope
    The study uses first-order CPA on the first AES S-box round on a CW305 Artix-7 platform; results should not be generalized beyond that setup without qualification.

  5. BOOK CHAPTER2024

    Applied Reconfigurable Computing (ARC), LNCS, Springer, pp. 255–266, 2024 · DOI 10.1007/978-3-031-55673-9_18

    Chapter PDF · pp. 255–266 DOI / publisher AI paper memory
    Paper explanation and citation context

    Core contribution. PROACT integrates resistance to side-channel and fault-injection attacks into the ASIC design flow, using a dual-RISC-V benchmark SoC and pre-silicon analysis to reduce physical-security iteration time.

    Reported status
    The 2024 chapter reports an FPGA prototype approaching tape-out, a simulator-based analysis workflow, and two planned tape-outs.
    Cite this for
    Physical-security-by-design, reduced time to market for protected circuits, the PROACT project, or its dual-RISC-V benchmark SoC.
    Scope
    This is a project-status chapter: planned tape-outs and intended evaluations must not be described as completed results. The local PDF contains only printed pages 255–266.

  6. SURVEY2023

    IEEE European Test Symposium (ETS), 2023 · DOI 10.1109/ETS56758.2023.10174099

    Read PDF DOI / publisher AI paper memory
    Paper explanation and citation context

    Core contribution. A cross-domain snapshot of RISC-V processor testability, safety, and security research, connecting manufacturing and in-field testing with functional safety, cryptographic extensions, side-channel protection, roots of trust, and trusted execution.

    Coverage
    The survey organizes SBST and system-level test, functional and timing safety, cryptographic hardware and ISA extensions, side-channel defenses, and hardware security foundations.
    Cite this for
    A broad 2023 overview of dependable and secure RISC-V processors or a taxonomy spanning testability, safety, and security.
    Scope
    It is a selected research snapshot rather than an exhaustive systematic review; the fast-moving RISC-V ecosystem may have evolved since publication.

  7. POSTER2026

    ACM Computing Frontiers (CF '26), pp. 341–342, 2026 · DOI 10.1145/3801487.3805609

    Read PDF DOI / publisher AI paper memory
    Paper explanation and citation context

    Core contribution. A concise CF '26 presentation of the same-platform comparison of AES side-channel countermeasures for RISC-V SoCs, emphasizing the measured security and implementation-cost trade-offs.

    Key evidence
    The poster summarizes baseline recovery at about 250 traces, no recovery for Mask-AES through 21,000 traces, and no recovery for Secure-Ibex through 18,000 traces, with their reported overheads.
    Cite this for
    The CF '26 poster record or a compact security-versus-cost summary of AES countermeasures on RISC-V SoCs.
    Scope
    This two-page poster presents the NorCAS experimental study concisely and should not be counted as an independent replication of that work.

// full list on Google Scholar

Education

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AUG 2022 – FEB 2027 · ONGOING

Ph.D. in Computer Science

Leiden University (LIACS), NL

Hardware security & digital IC design (PROACT). Dissertation: pre/post-silicon side-channel leakage evaluation in lightweight cryptographic circuits.

Thesis details →

2018 – 2021 · GPA 18.28/20

M.Sc. in Electrical Engineering — Digital Electronic Systems

University of Tehran · Ranked 1st in class

Thesis: ML-based modeling attacks on Physical Unclonable Functions (PUFs). Completed alongside a full-time research assistantship at the DVD-ES Lab.

Thesis details →

2014 – 2017 · GPA 16.87/20

B.Sc. in Electrical Engineering — Electronic Technology

Mohajer Technical University (MTU), Isfahan · Ranked 1st in the class of 2014

Thesis: real-time object detection & tracking on a Zynq-7000 SoC.

Thesis details →

2011 – 2013 · FULL SCHOLARSHIP

Associate Degree in Electronics

Amirkabir Technical & Vocational University of Markazi, Arak

Thesis: three-phase pure sine inverter — analog design with adjustable frequency, phase and amplitude.

Thesis details →

Theses

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PH.D.ONGOING

Pre/Post-Silicon Evaluation of Side-Channel Leakage in Lightweight Cryptographic Circuits

Leiden University (LIACS) · 2022 – 2027 (expected)

Pre- and post-silicon side-channel leakage evaluation across the PROACT SoC and ASSESS.

M.SC.2021 · Grade: Excellent

Implementation of Machine-Learning-based Attacks on PUF

University of Tehran

ML modeling attacks on RPUF and OBPUF, and SQ-PUF — a secure, scalable, ML-attack-resistant architecture.

B.SC.2016 · 19.75/20

Detection and Tracking of Moving Objects on the ZYNQ Platform

Mohajer Technical University of Isfahan

Real-time HDMI-in object detection and tracking on Zynq-7000, from MATLAB and OpenCV to HLS on silicon.

ASSOCIATE2013

Three-phase Pure Sine Inverter

Amirkabir Technical & Vocational University, Arak

Analog three-phase pure-sine inverter with adjustable frequency, phase and amplitude at 220 V output.

Honors & Awards

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  • 2020

    Ranked 1st in class (Digital Electronic Systems, cumulative GPA) · University of Tehran

  • 2018

    Ranked 102nd of 30,000+ · Iran nationwide M.Sc. entrance exam (electronics)

  • 2017

    Ranked 1st in the class of 2014 (cumulative GPA) · Mohajer Technical University

  • 2014

    Top 1% · nationwide Associate-to-Bachelor entrance exam (TVU)

  • 2013

    1st place, provincial stage · 14th National Skills Competition (WorldSkills, electronics)

  • 2012

    3rd place, provincial stage · National Scientific-Practical Competition (electronics)

  • 2010

    Diligent Student Award · Bozorgmehr Technical & Vocational School

LANGUAGES Persian (native) · English (professional working) · Dutch (A2)

Certifications & Badges

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Genus Physical Synthesis Flow v23.1

Cadence · 2024

verify on credly ↗

Artificial Intelligence & Machine Learning Fundamentals v1.0

Cadence · 2025

verify on credly ↗

Semiconductor 101 v1.0

Cadence · 2024

verify on credly ↗

Tcl Scripting for EDA v8.6

Cadence · 2025

download certificate (pdf) ↓

Cadence RTL-to-GDSII Flow v6.0

Cadence · 2025

download certificate (pdf) ↓

Technical Skills

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HARDWARE LANGUAGES
  • VHDL
  • Verilog
  • SystemVerilog
  • High-Level Synthesis (HLS)
PROGRAMMING
  • Python
  • C/C++
  • Tcl (EDA scripting)
ASIC FRONT-END
  • RTL design
  • RISC-V (Ibex) integration
  • Logic synthesis
  • SDC constraints
  • STA
  • Gate-level simulation
BACK-END
  • Place-and-route
  • Sign-off
  • GDSII
  • Bonding diagram (GF 22FDX)
VERIFICATION
  • RTL testbenches
  • Functional simulation
  • SDF-annotated gate-level simulation
  • FPGA validation
  • Hardware debugging
FPGA & EMBEDDED
  • Xilinx FPGAs
  • Vivado & Vivado HLS
  • Catapult HLS
  • SPI/UART
  • ESP32
  • AVR
HARDWARE SECURITY
  • CPA
  • DPA
  • TVLA
  • SNR/NICV
  • ChipWhisperer
  • Pre-silicon leakage analysis
  • PUFs
DESIGN METHODS
  • HW/SW co-design
  • Continuous integration (CI)
  • Design-for-test (DfT)
  • Fault-tolerant design
ML & EDA
  • Cadence (Genus, Joules, Xcelium)
  • Altium
  • MATLAB
  • PyTorch
  • PyTorch Geometric
  • scikit-learn
  • Keras
PARALLEL COMPUTING
  • CUDA
  • OpenMP
  • POSIX threads
  • SIMD

Teaching, Supervision & Activities

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Teaching
  • Teaching Assistant, System & Software Security, Leiden University (2022–present).
  • Earlier TA experience at the University of Tehran (2019–2022), including Chief TA for Core-based Embedded System Design and earlier TA courses.
Student supervision
  • Co-supervised 6+ B.Sc. theses on AES/RISC-V side-channel analysis and chip-prototype leakage assessment. Completed:
    • Imke van Ooijen — “Optimizing AES for RISC-V Cores” (2024)
    • Niels de Wit — “Power Leakage of AES Implementations” (2024)
    • Lennart van Drunick — “On the Vulnerabilities of FPGAs to Power Hammering Circuits” (2026)
    • Nathanael Mohanu — “Side-Channel Analysis of the PROACT Chip Prototype” (2026)
    • and further B.Sc. theses in progress.
Academic service
  • Reviewer, IEEE Transactions on Computer-Aided Design (TCAD).
Summer & training schools
  • CPS Summer School 2023 (Sardinia).
  • Real-World Crypto & Privacy 2023 (Croatia).
  • PROACT Hardware-Security Training Schools (2023, 2025).

Contact

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Open to roles in RTL/SoC design, HW/SW co-design, FPGA prototyping, ASIC physical design, or cryptographic hardware.

EMAIL a.sajadi@liacs.leidenuniv.nl PHONE +31 6 81183983 LINKEDIN linkedin.com/in/abisj GITHUB github.com/abolfazlsajadi ORCID 0000-0003-0657-7022 GOOGLE SCHOLAR Profile LEIDEN UNIVERSITY Staff page DOWNLOAD CV (PDF, 2 pages)