On Mon, 10 Aug 2026 04:00:38 +0800, guochun wang <[email protected]> wrote: > diff --git a/hw/gpio/k230_gpio.c b/hw/gpio/k230_gpio.c > new file mode 100644 > index 0000000000..9d27f0bbfd > --- /dev/null > +++ b/hw/gpio/k230_gpio.c > @@ -0,0 +1,362 @@ > [ ... skip 225 lines ... ] > + case K230_GPIO_PORTA_EOI: > + for (int i = 0; i < K230_GPIO_PINS_PER_GROUP; i++) { > + if (extract32(value, i, 1) && extract32(s->inttype_level, i, 1)) > { > + s->raw_intstatus = deposit32(s->raw_intstatus, i, 1, 0); > + } > + }
Hi Guochun Thanks for the patch. This is an addendum to Bin Meng's review, just for your reference. In the EOI path, the model only checks inttype_level[i] == 1 and does not check int_bothedge[i] == 1. With INTTYPE_LEVEL = 0, INT_POLARITY = *, INT_BOTHEDGE = 1, and the line enabled in INTEN / not masked by INTMASK, the interrupt status will be set on either edge but never cleared by EOI, so the IRQ line stays asserted. Could EOI clear when either inttype_level or int_bothedge is set? A qtest with INTTYPE_LEVEL=0 and INT_BOTHEDGE=1 would cover this path. Thanks, Junze > > diff --git a/include/hw/gpio/k230_gpio.h b/include/hw/gpio/k230_gpio.h > new file mode 100644 > index 0000000000..32005815d2 > --- /dev/null > +++ b/include/hw/gpio/k230_gpio.h > @@ -0,0 +1,71 @@ > [ ... skip 64 lines ... ] > + uint32_t config_reg1; > + > + qemu_irq irq[K230_GPIO_PINS_PER_GROUP]; > + qemu_irq output[K230_GPIO_PINS_PER_GROUP]; > +}; > + GPIO0 and GPIO1 are not symmetric in the real hardware: GPIO0 has only Port A, while GPIO1 has both Port A and Port B. Port A is 32 bits on both controllers, and Port B is 8 bits on GPIO1. The current model instantiates both controllers with the same 32-bit Port A only, so it cannot represent GPIO1's Port B / GPIO64-71. If the goal is to build a more generic Synopsys DesignWare APB GPIO model later, I'd suggest adding qdev properties such as porta_width and portb_width, and configuring them at instantiation: This is not strictly blocking the current SDK boot path, but it should be addressed if we want to support the full K230 GPIO range or keep the model reusable for other DW-style GPIOs. Thanks， Junze GPIO0: porta_width = 32, portb_width = 0 GPIO1: porta_width = 32, portb_width = 8 GPIO0: porta_width = 32, portb_width = 0 GPIO1: porta_width = 32, portb_width = 8 -- Junze Cao <[email protected]>
