th.lbib should format the same as th.lbia, and the other increment insns, with the address register in parenthesis.
Cc: [email protected] Fixes: 318df7238b9 ("disas/riscv: Add support for XThead* instructions") Reviewed-by: Alistair Francis <[email protected]> Signed-off-by: Richard Henderson <[email protected]> --- disas/riscv-xthead.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/disas/riscv-xthead.c b/disas/riscv-xthead.c index 428a6380e9..fbc96631fd 100644 --- a/disas/riscv-xthead.c +++ b/disas/riscv-xthead.c @@ -189,7 +189,7 @@ static const rv_opcode_data xthead_opcode_data[] = { { "th.mulsh", rv_codec_r, rv_fmt_rd_rs1_rs2 }, /* XTheadMemIdx */ { "th.lbia", rv_codec_r2_imm2_imm5, rv_fmt_rd_rs1_immh_imml_addr }, - { "th.lbib", rv_codec_r2_imm2_imm5, rv_fmt_rd_rs1_immh_imml }, + { "th.lbib", rv_codec_r2_imm2_imm5, rv_fmt_rd_rs1_immh_imml_addr }, { "th.lbuia", rv_codec_r2_imm2_imm5, rv_fmt_rd_rs1_immh_imml_addr }, { "th.lbuib", rv_codec_r2_imm2_imm5, rv_fmt_rd_rs1_immh_imml_addr }, { "th.lhia", rv_codec_r2_imm2_imm5, rv_fmt_rd_rs1_immh_imml_addr }, -- 2.43.0
